The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.
The decreased geometry sizes lead to challenges in semiconductor fabrication. For example, as geometry sizes continue to decrease, fabrication process tolerances are reduced, and the impact from wafer topography variations will limit process windows such as lithography or etching process windows. Traditional fabrication process schemes have not sufficiently addressed these issues caused by wafer topography variations.
Therefore, while traditional lithography methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.